1. Field of the Invention
The present invention relates to a ferroelectric random access memory using a ferroelectric capacitor, and in particular, to a ferroelectric random access memory having a remedial redundancy function.
2. Description of the Related Art
Ferroelectric random access memories (FeRAMs) using a ferroelectric capacitor are known as nonvolatile semiconductor storage devices. Chain FeRAMs (TMs) are also known, as disclosed in Jpn. Pat. Appln. KOKAI Publication Nos. 10-255483, 11-177036, and 2000-22010. In the chain FeRAM, a cell transistor and a ferroelectric capacitor are arranged in parallel to constitute one unit cell. Moreover, a plurality of unit cells is connected in series to constitute a memory cell block. The chain FeRAM serves to realize small-sized memory cells, planar transistors that are easy to manufacture, and a general-purpose high-speed random access function.
For the chain FeRAM, it is important to acquire a chip with a large signal amount in order to ensure reliability. To obtain a sufficient signal amount, it is effective to operate the memory using a pulse signal with a somewhat large pulse widely. When a large number of unit cells are connected in series in a memory cell block, a longer time is required to apply a desired potential to the cells. This affects the signal amount, preventing an increase in operating speed.
On the other hand, semiconductor storage devices generally have a remedial redundancy function. With this function, when any of the main cells are defected, the defected cell is replaced with a redundancy cell to improve yield. The chain FeRAM also has a redundancy memory cell block to provide a remedial redundancy function.
However, a redundancy region in which the redundancy memory cell block is formed is normally located at an end of a cell array. The location at the cell array end may degrade the characteristics of the unit cells in the redundancy memory cell block compared to those of main unit cells that have not been replaced. When the unit cells in the redundancy memory cell block have bad characteristics, remedy efficiency may decrease.
Further, even with successful remedy, the use of the redundancy region may degrade the capabilities of the chip. In a conventional chain FeRAM disclosed in, for example, FIG. 40 of Jpn. Pat. Appln. KOKAI Publication No. 10-255483, as many unit cells as those connected in series in a main memory cell block are connected in series in a redundancy memory cell block. One end of the redundancy memory cell block is connected to a bit line via a block selecting transistor. The other end is connected to a spare plate line.
In the chain FeRAM, when data is read from a selected unit cell, the corresponding bit line is set to a low potential, for example, zero. The corresponding plate line is boosted from the low potential to a high potential, for example, 3 V. On the other hand, when data is written to a selected unit cell, then one of the corresponding bit and plate lines is set to a low potential, for example, zero depending on the write data. The other is set to a high potential, for example, 3 V.
When data is read from one of a plurality of unit cells in a redundancy memory cell block which is located furthest from the corresponding bit line, the polarization state of the selected cell is read to the bit line via a large number of cell transistors. This reduces the speed at which signals are read from the selected cell. On the other hand, when data, particularly “1” data, is written to the unit cell located furthest from the bit line, a potential of 3 V applied to the bit line is transmitted to the selected cell via a large number of cell transistors. This reduces the time for which the write potential is applied to a ferroelectric capacitor in the selected cell. The write operation is thus insufficient.
When data is read from the unit cell located furthest from the plate line, a potential of 3 V applied to the plate line is transmitted to the selected cell via a large number of cell transistors. This also reduces the speed at which signals are read from the selected cell. On the other hand, when data is written to the unit cell located furthest from the plate line, writing “0” data involves transmitting a potential of zero applied to the plate line to the selected cell via a large number of cell transistors. This reduces the time for which the write potential is applied to the ferroelectric capacitor in the selected cell. Writing “1” data involves transmitting a potential of 3 V applied to the plate line to the selected cell via a large number of cell transistors. This reduces the time for which the write potential is applied to the ferroelectric capacitor in the selected cell. That is, when data is written to the unit cell located furthest from the plate line, the write operation is insufficient for both “0” and “1” data.
Jpn. Pat. Appln. KOKAI Publication No. 6-203594 discloses a static RAM having a redundancy function that enables a replacement unit to be set for a redundancy memory part.